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? semiconductor components industries, llc, 2016 october, 2016 ? rev. 0 1 publication order number: ncv8856/d ncv8856 automotive grade synchronous buck controller the ncv8856 is an adjustable output, synchronous buck controller, which drives dual n?channel mosfets, ideal for high power applications. average current mode control is employed for very fast transient response and tight regulation over wide input voltage and output load ranges. the ic incorporates an internal fixed 6.0 v low?dropout linear regulator (ldo), which supplies charge to the switch mode power supply?s (smps) bottom gate driver, limiting the power lost to excess gate drive. the ic is designed for operation over an input voltage range of 4.5 v to 38 v and is capable of 10 to 1 voltage conversion at 500 khz. additional controller features include undervoltage lockout, overvoltage shutdown, internal soft?start, low quiescent current sleep mode, programmable frequency, sync function, average current limiting, cycle?by?cycle overcurrent protection and thermal shutdown. features ? average current mode control ? 0.8 v 2% reference voltage ? wide input voltage range of 4.5 v to 38 v ? operates through load dump conditions ? 6.0 v low?dropout linear regulator (ldo) ? input uvlo (undervoltage lockout) ? internal soft?start ? 1.0 a maximum quiescent current in sleep mode ? adaptive non?overlap circuitry ? 180 ns minimum high?side gate of f?time ? programmable fixed frequency ? 170 khz to 500 khz ? external clock synchronization up to 600 khz ? average current limiting (acl) ? cycle?by?cycle overcurrent protection (ocp) ? thermal shutdown (tsd) ? this is a pb?free device applications ? automotive systems requiring high current ? pre?regulated supply for low?voltage smpss and ldos www.onsemi.com marking diagram v8856 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package v88 56 alyw device package shipping ? ordering information tssop?20 ep suffix ab case 948ab (note: microdot may be in either location) NCV8856DBR2G tssop?20 ep (pb?free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncv8856 www.onsemi.com 2 v clamp figure 1. functional block diagram figure 2. application schematic v in en v in_ic sync r osc c comp 12 11 c fb cs out v comp v fb 20 1 3 15 16 17 14 13 9 6v out bst gh v sw 4 5 6 7 8 2 19 18 10 gl pgnd v in_cs csp csn agnd csa fault acl bst 6v out fault v acl + + v ref v ss + vea cea ocp v ocp nonoverlap + v ref pwm tsd enable uvlo fixed?frequency oscillator ramp clock max duty reset dominant fault logic ldo enable ldo i limit soft start v ss min on time q q s r 12 11 3 1 20 r osc r osc sync v in_ic en v in 15 16 17 10 v in c c2 c comp c c1 r c1 r c2 cs out agnd c fb 14 13 18 19 2 8 7 6 5 4 9 l c + + ? v out r s r v1 c v1 c v2 v comp v fb csn csp r f1 r f0 pgnd v in_cs gl v sw gh bst 6v out d bst v in + + ? c bst q1 q2 note: this part is recommended for synchronous use only.
ncv8856 www.onsemi.com 3 package pin descriptions ? 20 lead tssop package pin# pin symbol function 1 sync external clock synchronization input. 2 v in_cs supply input for the internal current sense amplifier. 3 v in_ic supply input for internal logic and analog circuitry. 4 bst supply input for the floating top gate driver. an external diode, d bst , from 6v out and a 0.1 f to 1 f capacitor, c bst , to v sw forms a boost circuit. 5 gh gate driver output for the external high?side nmos fet. 6 v sw switch?node. this pin connects to the source of the high?side mosfet and drain of the low?side mosfet. this pin serves as the switch output to the inductor. 7 gl gate driver output for the external low?side nmos fet. 8 pgnd power ground. ground reference for the high?current path including the nmos fets and output capacitor. 9 6v out output of internal fixed 6.0 v ldo. 10 agnd analog ground. ground reference for the internal logic and analog circuitry as well as r osc and the compensators. 11 en enable input. when disabled, the ldo, internal logic and analog circuitry and gate drivers enter sleep mode, drawing under 1 a. 12 v in supply input for the smps. 13 v fb smps?s voltage feedback. inverting input to the voltage error amplifier. connect to v out through a resistive divider. 14 v comp smps?s voltage error amplifier output and non?inverting input to the current error amplifier. 15 c comp smps?s current error amplifier output and inverting input to the pwm comparator. 16 c fb smps?s current feedback. inverting input to the current error amplifier. 17 cs out single?ended output of the differential current sense amplifier. connect to c fb through a resistor. non?inverting input to the cycle?by?cycle overcurrent comparator. 18 csn differential current sense amplifier inverting input. 19 csp differential current sense amplifier non?inverting input. 20 r osc oscillator?s frequency adjust pin. resistor to ground sets the oscillator frequency.
ncv8856 www.onsemi.com 4 maximum ratings (voltages are with respect to gnd unless otherwise indicated.) (note 1) rating symbol value unit dc supply voltage peak transient voltage (load dump, en = 0 v) en, v in , v in_cs ?0.3 to 40 45 v dc supply voltage v in_ic 6.5 v pin voltage t 50 ns v sw ?0.3 to 38 ?2 v pin voltage bst, gh ?0.3 to 44 ?0.3 to 6 wrt v sw v pin voltage gl ?0.3 to 7 wrt pgnd v pin voltage csp, csn ?0.3 to 10 v pin voltage v fb , v comp , cs out , c fb , c comp , sync, r osc , 6v out ?0.3 to 7 v operating junction temperature t j(max) ?40 to 150 c storage temperature range t stg ?65 to 150 c esd capability, human body model (note 2) esd hbm 2 kv moisture sensitivity level msl 1 lead soldering temperature reflow (smd styles only), pb?free versions (note 3) t sld 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec?q100?002 (eia/jesd22?a114) 3. for information, please refer to our soldering and mounting techniques reference manual, solderrm/d thermal characteristics rating symbol value unit thermal characteristics (note 4) thermal resistance, junction?to?ambient (note 5) thermal resistance, junction?to?lead2 (note 6) r ja r jl 156 108 c/w 4. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 5. values based on copper area of 50 mm 2 of 1 oz copper on fr4 board. 6. values based on copper area of 645 mm 2 of 1 oz copper on fr4 board.
ncv8856 www.onsemi.com 5 electrical characteristics (?40 c < t j < 150 c, 4.5 v < v in < 38 v, 4.5 v < bst < v bst = v sw + 6 v, r osc = 51.1 k , unless otherwise specified) characteristic conditions symbol min typ max unit general quiescent current (i vin + i vin_cs + i bst ) v in = 13.2 v, en = 0 v, sleep mode ?40 c < t a < 125 c i q,sleep ? ? 1 a v in = 13.2 v, v fb = 1 v en = 5 v, no switching i q2 ? 2.0 3.0 ma v in = 13.2 v, v fb = 0 v en = 5 v, switching i q3 1 3.2 6.0 ma ldo current v in = 13.2 v, v fb = 0 v, en = 5 v switching, 3.3 nf on gh and gl i ldo 1 10 20 ma thermal shutdown guaranteed by design t sd 150 180 210 c thermal shutdown hysteresis guaranteed by design t sd,hys 1 10 20 c undervoltage lockout (v in_ic ) v in_ic increasing v in_ic decreasing v uvlo 4.1 3.9 4.3 4.18 4.5 4.45 v undervoltage lockout hysteresis v uvhy 50 125 200 mv switching regulator reference voltage v ref 0.784 0.8 0.816 v minimum gh off time t on/mon 110 180 250 ns minimum gh pulse width static operating t p, m i n ? 140 200 ns oscillator switching frequency r osc = 51.1 k r osc = 23.2 k r osc = 16.2 k f rosc 153 306 425 170 360 500 187 414 575 khz ramp voltage amplitude v ramp 0.9 1.1 1.3 v voltage error amplifier dc gain guaranteed by design a vea 70 73 ? db gain?bandwidth product guaranteed by design bw vea 8.0 10 ? mhz charge currents source, v comp = 0 v i vea,so 2 4 ? ma sink, v comp = 1.75 v i vea,si 1.3 3 ? ma fb bias current guaranteed by design i vea,bias ? 0.1 1.0 a current sense amplifier common?mode range v cmr 0 ? 10.0 v amplifier gain 0 (csp?csn) 100 mv 0 v csn 10.0 v g csa ? 1 ? v/v current error amplifier dc gain guaranteed by design a csa 70 73 ? db gain?bandwidth product guaranteed by design bw csa 8.0 10 ? mhz charge currents source, c comp = 1.75 v i csa,so 2 4 ? ma sink, c comp = 1.75 v i csa,si 1.3 3 ? ma fb bias current guaranteed by design i csa,bias ? 0.1 1.0 a clamping voltage v csa,clp 2.7 3.5 ? v
ncv8856 www.onsemi.com 6 electrical characteristics (?40 c < t j < 150 c, 4.5 v < v in < 38 v, 4.5 v < bst < v bst = v sw + 6 v, r osc = 51.1 k , unless otherwise specified) characteristic unit max typ min symbol conditions current limit average current limit threshold 1.2 v csn 10.0 v v ilim,av 80 100 125 mv cycle?by?cycle current limit threshold voltage v ilimpk 115 165 215 mv cycle?by?cycle current limit response time guaranteed by design t lim ? 200 ? ns cycle?by?cycle and average cur- rent limit threshold difference v lim,th 20 ? ? mv sync sync frequency range f sw is defined by r osc switching frequency f sync f sw ? 600 khz sync pin bias current v sync = 0 v v sync = 5.0 v f sync,bias ? ? 0.1 10 0.2 20 a sync threshold voltage logic low logic high v sync,l v sync,h ? 2.0 ? ? 0.8 ? v 6.0 v ldo output voltage i out = 20 ma v ldo 5.8 6.0 6.2 v dropout voltage i out = 20 ma v ldo,do ? ? 200 mv current limit i ldo,cl 30 75 120 ma gate drivers gh sink current v gh = 2 v, v in_ic = 6 v, guaranteed by design v gh = 4 v, v in_ic = 6 v, guaranteed by design i gh,src 1 1.5 2 a gh source current i gh,srv 1 1.5 2 a gl sink current v in_ic = 6 v v gl = 1.0 v guaranteed by design i gl,sync 1 1.5 2 a gl source current i gl,src 1 1.5 2 a gh to gl delay v in = 13.2 v t ghgl,d ? 40 70 ns gl to gh delay v in = 13.2 v t glgh,d ? 40 70 ns soft start time f sw = 170 khz t ss ? 14 ? ms enable (en) input threshold logic low logic high v enlo v enhi ? 2.0 ? ? 0.8 ? v input current en = 2.0 v i en,i ? 3.0 10 a minimum disable time t en,dis ? ? 20 ms product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncv8856 www.onsemi.com 7 typical characteristics (t a = +25 c, v in = 13.2 v, r osc = 51.1 k , unless otherwise noted) 30% 40% 50% 60% 70% 80% 90% 100% 170 220 270 320 370 420 470 switching frequency (khz) soft start time (%) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 170 220 270 320 370 420 470 switching frequency (khz) driver current (ma) 8 10 12 14 16 18 20 01234 load capacitance (nf) fall time (ns) top gate bottom gate 8 13 18 23 28 33 38 01234 load capacitance (nf) rise time (ns) top gate bottom gate 45% 55% 65% 75% 85% 95% 105% ?50 0 50 100 150 ambient temperature ( c) operating current (%) switching no switching 98% 99% 100% 101% ?50 0 50 100 150 ambient temperature ( c) average current limit threshold (%) 97% 98% 99% 100% 101% ?50 0 50 100 150 ambient temperature ( c) cycle?by?cycle ocp threshold (%) 99.0% 99.5% 100.0% 100.5% ?50 0 50 100 150 ambient temperature ( c) v figure 3. soft?start time vs. frequency figure 4. driver quiescent current vs. frequency figure 5. driver fall time vs. load capacitance figure 6. driver rise time vs. load capacitance figure 7. operating quiescent current vs. temperature figure 8. sleep mode quiescent current vs. temperature figure 9. average current?limit threshold vs. temperature figure 10. cycle?by?cycle overcurrent protection threshold vs. temperature figure 11. v ref vs. temperature 0 0.2 0.4 0.6 0.8 1 ?50 0 50 100 150 ambient temperature ( c) shutdown current ( a) ref
ncv8856 www.onsemi.com 8 typical characteristics (t a = +25 c, v in = 13.2 v, r osc = 51.1 k , unless otherwise noted) 96% 97% 98% 99% 100% 101% 102% ?50 0 50 100 150 ambient temperature ( c) switching frequency (%) 170 khz 360 khz 500 khz 20 25 30 35 40 45 50 55 60 65 70 ?50 0 50 100 150 ambient temperature ( c) delay (ns) gh to gl gl to gh 98% 100% 102% 104% 106% 108% ?50 0 50 100 150 ambient temperature ( c) minimum pulse width (%) 99.50% 99.75% 100.00% 100.25% 100.50% 0.00 5.00 10.00 15.00 20.00 ldo load current (ma) 6v out (v) 0.1 1 10 100 1000 0 5 10 15 20 ldo load current (ma) output capacitor esr ( ) unstable unstable (0.1uf only) stable 50 60 70 80 90 100 110 120 130 ?50 0 50 100 150 ambient temperature ( c) dropout voltage (mv) 93% 0 20 40 60 80 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 load current (a) efficiency (%) figure 12. oscillator frequency vs. temperature figure 13. non?overlap delay vs. temperature figure 14. gh minimum pulse width vs. temperature figure 15. ldo load regulation figure 16. ldo stability region figure 17. ldo dropout voltage vs. temperature figure 18. efficiency vs. load current 5 v, 170 khz demo board
ncv8856 www.onsemi.com 9 detailed operating description general the ncv8856 is a synchronous buck controller with internal 1.5 a gate drivers designed to drive nmos fets. the internal gate drivers simplify design, improve performance and efficiency and minimize board area. the controller uses an 800 mv, 2.0% reference, allowing for a wide range of precise output voltage programmability. the ncv8856 also provides a programmable fixed frequency range of 170 khz to 500 khz, allowing more design flexibility in compromising efficiency versus components? size and cost. this frequency is conveniently set with an external resistor to ground. an external clock signal can also be used to synchronize the ncv8856 to a higher operating frequency during operation. to protect against possible damage of external power?stage components, excessive inrush of current during start?up is prevented by an internal soft?start, and inductor current is limited via average current limiting (acl) and cycle?by?cycle overcurrent protection (ocp). thermal shutdown (tsd) is also implemented to protect the device from overheating. average current mode control the ncv8856 employs an average current mode control (acmc) architecture to regulate the output voltage. acmc uses two loops, as seen in figure 19. through the current error amplifier (cea), the inner current loop monitors the inductor current with the unity gain current sense amplifier (csa). the current loop responds to input voltage changes, affecting the line transient response. using the voltage error amplifier (vea), the outer voltage loop monitors the output voltage, responding to output load changes, affecting the load transient response. feedback resistors in the voltage loop select the output voltage. l ? + csa ? + vea ? + cea c pwm and gate drivers inner current loop outer voltage loop gain=1 figure 19. acmc loops v sw r s r l v out v ref unlike voltage mode control (vmc) of buck regulators, which almost always require the extra components of a type?iii compensation network for adequate transient response, acmc buck regulators use t ype?ii compensation. this greatly simplifies the compensator design and optimization process, while offering much faster transient response than a type?i compensation network. additionally, the two?loop system separates the effects of output components between the two loops, further simplifying the compensation process. type?ii compensation places a zero and two poles in each of the error loops to offset the effects of the inherent open?loop response. this compensation requires a resistor and two capacitors in the feedback loop for each of the error amplifiers, shown as complex impedances in figure 19. an input resistor from the csa to the cea sets the gain of the cea. the voltage loop also has a pair of feedback resistors from v out to set the output voltage and gain of the vea. enable the enable input (en) is a ttl?compatible input used to activate the internal ldo. the ncv8856 is disabled when the en pin is pulled below the enable input logic low threshold voltage, causing a normal shutdown to occur, putting the part into a low quiescent current sleep mode. once the device has been disabled it must remain disabled for the minimum disable time (20 ms) or abnormal startup behavior may be observed after enable is asserted. when the en pin is pulled above the enable input logic high threshold voltage, the part is enabled, the ldo output is brought up and then the internal soft?start begins.
ncv8856 www.onsemi.com 10 en 125 k 22 v 5.4 v internal enable figure 20. enable pin equivalent structure r en v in d zen2 d zen1 the en pin can be tied to v in in order to enable the part. if en is above 22 v, d zen2 will be conducting, as well as d zen1 . the current to d zen1 is limited by an internal 125 k resistor. if d zen2 is conducting, it is recommended at least 250 a is pulled through this diode. the resistor r en must be used if v in can go above 20 v as follows. r en(max) v z 250 a where v z is the amount of volts where d zen2 is conducting, but not yet supplied with 250 a. for example, setting v z to 1 v means r en must be less than 4 k for d zen2 to have at least 250 a when v in is at least 23 v; for the range of v in between 22 v and 23 v, d zen2 will be conducting, but not with the recommended 250 a current. uvlo undervoltage lockout (uvlo) is provided to ensure that unexpected behavior does not occur when v in_ic is too low to support the internal rails and power the controller. the ic will start up when enabled and v in_ic surpasses the uvlo threshold and will shutdown when v in_ic drops below the uvlo threshold minus the uvlo hysteresis. while v in is less than the set point for v out , the output will run at max duty cycle, after soft?start, once v in_ic surpasses the uvlo threshold. if en is high and not tied to v in , the output will begin to rise up while in uvlo, if a minimum output load of 1 k is not met. thermal shutdown the ncv8856 provides thermal shutdown (tsd), which monitors the die temperature and turns off the top and bottom gate drivers if an over temperature condition is detected, for added protection. the internal soft?start capacitor is also discharg ed. a normal soft?start will occur when the die temperature falls below the tsd threshold minus the tsd hysteresis. duty cycle and maximum pulse width limits in steady state dc operation, the duty cycle will stabilize at an operating point defined by the ratio of the input to the output voltage. there is a built in minimum off?time which ensures that the bootstrap supply is charged every cycle, determining the maximum duty cycle at a given frequency. the ncv8851 can achieve at least a 95% duty cycle while operating at frequencies up to 200 khz (89% at up to 500 khz). internal soft?start the ncv8856 features an internal soft?start function, which reduces inrush current and overshoot of the output voltage. figures 21 and 22 show a typical soft?start sequence. uvlo threshold figure 21. normal start?up figure 22. switch?node in soft?start v sw t soft?start time 90%*v out 10%*v out soft?start delay v in v out t 6v out and v in_ic soft?start is achieved by ramping up the internal soft?start voltage (v ss ), which is applied to the non?inverting input of the voltage error amplifier, effectively limiting the slew rate of v out rising. this ramp is generated by charging an internal soft?start capacitor based on the internal oscillator, causing the soft?start time to be inversely related to the frequency set by r osc . the internal soft?start capacitor is discharged when the part is disabled, enters tsd or enters uvlo, ensuring a proper start?up when the part is re?enabled, leaves tsd or leaves uvlo.
ncv8856 www.onsemi.com 11 this sequence begins once v in_ic surpasses its uvlo threshold when the part is enabled and the ldo output has risen. after an initial delay to assure a clean start?up, switching begins, the output initially rises quickly and then rises monotonically. the duty cycle is gradually increased until v out has reached its set point or until maximum duty cycle is reached. normal shutdown behavior and sleep mode normal shutdown occurs when the ic stops switching because the input supply drops below the uvlo threshold, the part enters tsd or the part is disabled. when disabled, the part enters sleep mode. in sleep mode, the ldo turns off and its output capacitor discharges, causing switching to stop, the internal soft?start capacitor to discharge and gh and gl to go low. the switch node enters a high impedance state and the output inductor and capacitors discharge through the load. the supply current reduces to the sleep mode quiescent current. internal linear regulator (ldo) the ncv8856 has an onboard low?dropout linear regulator (ldo) internally connected to drive the low?side gate. the 6v out pin should be externally connected to the v in_ic pin to power the internal rails. typically, a rc filter is used from 6v out to v in_ic to further decrease noise on the internal rails. the 6v out pin should be externally connected through a low leakage (< 100 a at t max ) diode to the bst pin, charging the bst capacitor during off?time to generate a voltage for the high?side driver. when the part is enabled and v in is below the ldo regulated value, the ldo is in dropout and it tracks v in . the ldo regulates its output once v in is above the output set point plus the dropout voltage. an external bypass capacitor must be connected from 6v out to ground. a short to ground or overcurrent condition on the 6v out pin will be mitigated by the ldo current limit and internal thermal shutdown (tsd) circuitry which disables all outputs. a normal soft?start will occur when the die temperature falls below the tsd threshold. drivers the ncv8856 includes 1.5 a gate drivers to switch external n?channel mosfets. this al lows the ncv8856 to address high?power, as well as low?power conversion requirements. the gate drivers also include adaptive non?overlap circuitry. the non?overlap circuitry increases efficiency, which minimizes power dissipation, by minimizing the body diode conduction time, while protecting against cross?conduction (shoot?through) of the mosfets. a detailed block diagram of the non?overlap and gate drive circuitry used in the chip and related external components is shown in figure 23. pgnd gh gl bst main pwm output mainfault gl threshold threshold gl to gh delay gh to gl delay figure 23. gate driver block diagram fault v sw v sw v sw 6v out a capacitor is placed from v sw to bst and a diode is placed from 6v out to bst to create a bootstrap supply on the bst pin for the high?side floating gate driver. this ensures that the voltage on bst is about 6v out higher than v sw , less a diode drop, yielding a gate drive voltage high enough to enhance the high?side mosfet. the bst capacitor supplies the charge used by the gate driver to charge up the input capacitance of the high?side mosfet, and is typically chosen to be at least a decade larger than this capacitance. a 0.1 f bst capacitor is recommended. since the bst capacitor only recharges when the low?side mosfet is on, pulling v sw down to ground, the ncv8856 has a mi nimum of f?time. this also means that the bst capacitor cannot be arbitrarily large, since 6v out needs to be able to charge it up during this minimum off?time so the high?side gate driver doesn?t run out of headroom. 6v out needs to supply charge both to the bst capacitor and also the low?side driver, so the ldo capacitor must be sufficiently larger than the bst capacitor. a 1 f ldo capacitor is recommended.
ncv8856 www.onsemi.com 12 careful selection and layout of external components is required to realize the full benefit of the onboard drivers. the capacitors between v in and gnd and between bst and v sw must be placed as close as possible to the ic. the current paths for the gh and gl connections must be optimized, minimizing parasitic resistance and inductance. current limiting and overcurrent protection the ncv8856 contains average current limiting (acl) and cycle?by?cycle overcurrent protection (ocp) to protect the power switches, inductor, current sense resistor and other external components. the current through the inductor is continuously sensed using the csp and csn pins. a sense resistor is placed between these pins to translate the output current to a proportional voltage. this voltage is compared to a fixed internal voltage threshold. when the dif ferential voltage exceeds the acl threshold, the pwm pulse is terminated for this cycle, limiting the current through the inductor. in steady?state operation, decreasing the load resistance while in acl will cause the duty cycle and v out to decrease proportionally without skipping pulses or jitter. there is also a fast ocp path which is tripped when the differential voltage exceeds the ocp threshold, which is above the acl threshold. this causes the pwm pulse to be terminated very quickly and disables the part from switching back on until the current through the inductor has dropped below the ocp threshold. once the inductor current is below the ocp threshold, the part will begin switching again and the current will be limited by acl, until the inductor current drops below the acl threshold. an advantage of this current limiting scheme is that the ncv8851 will limit large transient currents yet resume normal operation on the following cycle. additionally, the current will not run away, nor will the part latch off in case of a short, which is typical of other current limiting schemes employing high?side current sensing. sync feature an external clock signal can synchronize the ncv8856 to a higher frequency. the rising edge of the sync pulse turns on the power switch to start a new switching cycle, as shown in figure 24. there is a 0.5 s delay between the rising edge of the sync pulse and rising edge of the v sw pin voltage. the sync threshold is ttl logic compatible, and duty cycle of the sync pulses can vary from 10% to 90%. the sync frequency must be higher than the internal oscillator frequency set by r osc . figure 24. synchronization from 170 khz to an external 600 khz signal
ncv8856 www.onsemi.com 13 applications information design methodology choosing external components for the ncv8856 encompasses the following design process: 1. define operational parameters 2. select switching frequency 3. select current sensor 4. select output inductor 5. select output capacitors 6. select input capacitors 7. select compensator components (1) operational parameter definition before proceeding with the rest of the design, certain operational parameters must be defined. these are application?dependent and include the following: v in : input voltage, range from minimum to maximum with a typical value [v] v out : output voltage [v] i out : output current, range from minimum to maximum with initial start?up value [a] i cl : desired typical current?limit [a] a number of basic calculations must be performed up?front to use in the design process, as follows: d min v out v in(max) d v out v in(typ) d max v out v in(min) where: d min : minimum duty cycle (ideal) [%] v in(max) : maximum input voltage [v] d: typical duty cycle (ideal) [%] v in(typ) : typical input voltage [v] d max : maximum duty cycle (ideal) [%] v in(min) : minimum input voltage [v] it should be noted that these are the ideal duty cycles; the actual duty cycles will be marginally higher than these calculated values. the actual duty cycles are dependent on load due to voltage drops in the mosfets, inductor and current sensor. (2) switching frequency selection selecting the switching frequency is a trade?of f between component size and power losses. operation at higher switching frequencies allows the use of smaller inductor and capacitor values to achieve the same inductor current ripple and output voltage ripple. however, increasing the frequency increases the switching losses of the mosfets, leading to decreased ef ficiency, especially noticeable at light loads. typically, the switching frequency is selected to avoid interfering with signals of known frequencies. often, in this case, the frequency can be programmed to a lower value with r osc and then a higher?frequency signal can be applied to the sync pin to increase the frequency dynamically to avoid given frequencies. a spread spectrum signal could also be used for the sync input, as long as the lowest frequency in the range is above the programmed frequency set by r osc . additionally, the highest sync frequency must not exceed maximum switching frequency limits. there are two limits on the maximum allowable switching frequency: minimum off?time and minimum on?time. these set two dif ferent maximum switching frequencies, as follows: f sw(max)1 1 d max t minoff f sw(max)2 d min t minon where: f sw(max)1 : maximum switching frequency due to minimum of f?time [hz] t minoff : minimum of f?time [s] f sw(max)2 : maximum switching frequency due to minimum on?time [hz] t minon : minimum on?time [s] alternatively, the minimum and maximum operational input voltage can be calculated as follows: v in(min) v out 1 t minoff f sw v in(max) v out t minon f sw where: f sw : switching frequency [hz] the switching frequency is programmed by selecting the resistor connected between the r osc pin and ground. the grounded side of this resistor should be directly connected to the agnd pin. avoid running any noisy signals under the resistor, since injected noise could cause frequency jitter. the graph in figure 25 shows the required resistance to program the frequency. from 150 to 450 khz, the following formula is accurate to within 3%: r osc 8687000 f sw where: r osc : frequency program resistor [ ] some specific values for switching frequency with standard 1% resistors can be seen in table 1.
ncv8856 www.onsemi.com 14 0 100 200 300 400 500 600 10 20 30 40 50 60 70 80 90 r osc (k ) figure 25. frequency vs. r osc f sw (khz) table 1. frequency vs. r osc f sw (khz) r osc (k ) 170 51.1 250 34.8 300 28.7 360 23.2 500 16.2 the soft?start time can be estimated as follows: t ss f 0 f sw t ss0 where: t ss : soft?start time [s] f 0 : specified frequency [hz] t ss0 : soft?start time at specified frequency [s] (3) current sensor selection current sensing for average current mode control relies on the inductor current signal. this is translated into a voltage via a current sensor, which is then measured dif ferentially by the current sense amplifier, generating a single?ended output to use as a control signal. the easiest means of implementing this transresistance is through the use of a sense resistor in series with the output inductor and capacitors. a sense resistor should be selected as follows: r s v cl i cl where: r s : sense resistor [ ] v cl : current limit threshold voltage [v] i cl : desired current limit [a] alternative methods, such as lossless inductor current sensing, are feasible but beyond the scope of this document. (4) output inductor selection both mechanical and electrical considerations influence the selection of an output inductor. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the largest components in the power supply, a minimum inductor value is particularly important in space? constrained applications. from an electrical perspective, an inductor is chosen for a set amount of current ripple and to assure adequate transient response. larger inductor values limit the switcher?s ability to slew current through the output inductor in response to output load transients, impacting the dynamic response. while the inductor is slewing current during this time, output capacitors must supply the load current. therefore, decreasing the inductance allows for less output capacitance to hold the output voltage up during a load step. load transient simulation is a powerful tool in anticipating this response. for switchers with both cycle?by?cycle overcurrent protection (ocp) and average current limiting (acl), the ocp and acl references are compared to the sensed current via sense resistance, r s . a minimum inductance is required to prevent the ocp from tripping during the onset of acl during typical operation as follows: l min v out (1 d) 2 f sw r s v cl where: l min : minimum inductance to assure ocp and acl do not both trip [h] v cl : difference between ocp and acl threshold voltages [v] for switchers that use the current signal of the inductor for control purposes, the voltage ripple over the sense resistance must be sufficient in magnitude to counteract the contribution due to inherent comparator offsets and other errors, as follows: l max v out (1 d max ) f sw r s l v cl where: l max : maximum inductance to assure adequate voltage ripple over the sense resistance [h] l : inductor peak?to?peak current ripple to current limit ratio [%] v cl : threshold voltage for the current limit [v] as a rule of thumb, ensuring that l is at least 5% to 10% has been empirically sufficient. smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current, which causes higher output voltage ripple. the peak?to?peak ripple current is given by the following equation: i l v out (1 d) l f sw where: i l : peak?to?peak output current ripple [app]
ncv8856 www.onsemi.com 15 the ripple current is at a maximum when the duty cycle is at a minimum value and vice versa, as follows: i l(max) v out (1 d min ) l f sw i l(min) v out (1 d max ) l f sw where: i l(max) : maximum inductor current ripple [app] i l(min) : minimum inductor current ripple [app] from this equation it is clear that the ripple current increases as l decreases, emphasizing the trade?off between dynamic response and ripple current. the peak and valley values of the triangular current waveform are as follows: i l(pk) i out i l 2 i l(vly) i out i l 2 where: i l(pk) : peak (maximum) value of ripple current [a] i l(vly) : valley (minimum) value of ripple current [a] saturation current is specified by inductor manufacturers as the current at which the inductance value has dropped a certain percentage from the nominal value, typically 10%. for stable operation, the output inductor must be chosen so that the inductance is close to the nominal value even at the peak output current, i l(pk) . it is recommended to choose an inductor with saturation current sufficiently higher than the peak output current, such that the inductance is very close to the nominal value at the peak output current. this introduces a safety factor and allows for more optimized compensation. inductor efficiency is another consideration when selecting an output inductor. inductor losses include dc and ac winding losses and core losses. core losses include eddy current losses, which are very low due to high core resistance, and magnetic hysteresis losses, which increase with peak?to?peak ripple current. core losses also increase as switching frequency increases. ac winding losses are based on the ac resistance of the winding and the rms ripple current through the inductor, which is much lower than the dc current. the ac winding losses are due to skin and proximity effects and are typically much less than the dc losses, but increase with frequency. dc winding losses account for a large percentage of output inductor losses and are the dominant factor at switching frequencies at or below 500 khz. the dc winding losses in the inductor can be calculated with the following equation: p l(dc) i out 2 r dc where: p l(dc) : dc winding losses in the output inductor r dc : dc resistance of the output inductor (dcr) as can be seen from the above equation, to minimize inductor losses, an inductor with very low dcr should be chosen. (5) output capacitor selection the output capacitor is a basic component for the fast response of the power supply. during a load step, for the first few microseconds, it supplies the current to the load. the controller immediately recognizes the load step and increases the duty cycle, but the current slope is limited by the inductor?s slew rate. during a load release, the output voltage will overshoot. the capacitance will dampen this undesirable response, decreasing the amount of voltage overshoot. in the case of stepping into a short, the inductor current approaches zero with the worst case initial current at the current limit and the initial voltage at the output voltage set point, calculating the voltage overshoot as follows: v os l i cl 2 c v out 2 v out accordingly, a minimum amount of capacitance can be chosen for a maximum allowed output voltage overshoot: c min l i cl 2 (v out v os(max) ) 2 v out 2 where: c min : minimum amount of capacitance to minimize voltage overshoot to v os(max) [f] v os(max) : maximum allowed voltage overshoot during a short [v] a maximum amount of capacitance can be found based on the inrush current and current limit. to calculate the input startup current, the following equation can be used: i inrush c out v out t ss i out(i) where: i inrush : input current during startup i out(i) : initial output current if the inrush current is higher than the steady?state input current with the maximum load, then the input fuse should be rated accordingly, if one is used. during soft?start, the inductor current must provide current to the load, as well as current to charge the output capacitor. the maximum current which the inductor is allowed to conduct is the current limit. setting the inrush current to the current limit, this puts a limit on the maximum capacitor size, as follows: c max (i cl i out(i) ) t ss v out where: c max : maximum output capacitance [f] capacitors should also be chosen to provide acceptable output voltage ripple with a dc load, in addition to limiting voltage overshoot during a dynamic response. key specifications are equivalent series resistance (esr) and equivalent series inductance (esl). the output capacitors must have very low esl for best transient response. the pcb traces will add to the esl, but by putting the output capacitors close to the load, this ef fect can be minimized and esl neglected in determining output voltage ripple.
ncv8856 www.onsemi.com 16 the capacitance itself causes a voltage ripple due to the current ripple. this is as follows: v q i l d c f sw where: v q : output voltage ripple due to output capacitance [vpp] also, the ripple current through the inductor causes a voltage ripple over the output capacitor due to its esr as follows: v esr i l r esr where: v esr : output voltage ripple due to the effects of esr [vpp] r esr : total esr of output capacitors [ ] typically, the ripple due to esr dominates, having the largest effect on output voltage ripple. the total output voltage ripple in steady?state operation can be calculated as follows: v out v q v esr c v out where: v out : total output voltage ripple [vpp] c : percent output voltage ripple [%] typically, the voltage ripple percentage is a performance parameter used to decide on the desired output capacitor. the maximum total effective esr of the output capacitors is calculated as follows: r esr(max) v out v q i l(max) where: r esr(max) : maximum allowable total esr of output capacitors it should be noted that these values of esr are at the switching frequency and esr decreases as frequency increases. the steady?state power lost due to the esr of the output capacitor can be calculated as follows: p c(esr) 1 3 i l 2 r esr (6) input capacitor selection the input capacitors have to sustain the ripple current produced during the on time of the high?side mosfet and must have a low esr to minimize the losses. the rms value of this ripple is: i in(rms) i out d (1 d) where: i in(rms) = input rms current the large majority of the ripple spectrum will be at the switching frequency. the above equation reaches its maximum value with d = 0.5, i in(rms) = i out /2. the input capacitors must be rated to handle a ripple current of one?half the maximum output current at the switching frequency. esr is the majority cause of losses in the input capacitors. losses in the input capacitors can be calculated with the following equation: p cin i in(rms) 2 r esr(cin) where: p cin = power loss in the input capacitors r esr(cin) = effective series resistance of the input capacitance due to large current transients through the input capacitors, electrolytic, polymer or ceramics should be used. if a tantalum must be used, it must be surge protected, to prevent against capacitor failure. due to the large ripple current, it is common to put small ceramic capacitors in parallel with the bulk input capacitors, which will handle a significant portion of the ripple current. a value of 0.01 f to 0.1 f placed near the mosfets is recommended. (7) compensator design the purpose of the compensators is to stabilize the dynamic response of the converter. by optimizing the compensators, stable regulation with fast input line and output load transient response is achieved. compensator design is related to the placement of zeros and poles in the closed loop, in order to assure stability with optimized transient response. the general approach is to use some rule of thumb values and then tune them through simulation to optimize load step response, while assuring stability over line and load variations. type?ii compensators are used with the two error amplifiers in average current mode control. the cea closes the inner current?loop and the vea closes the outer voltage?loop. as a rule of thumb, a zero is placed in each loop with the intent to compensate the effects of the double pole from the output inductor and capacitor. additionally, a pole is placed at origin, due to the negative feedback, and a pole is also placed in each loop with the intent to compensate the effects of the double right?half?plane zero from the current sampling function. the crossover frequency is then set so that gain limitations of the error amplifier are not exceeded. the compensator must assure there is adequate phase margin in the total closed?loop response, which can be analyzed on a small?signal basis. further reduction in loop gain, via decreasing the crossover frequency, may be required to avoid large?signal clamping limitations; this effect can be seen in simulation and taken care of in the compensator tuning process.
ncv8856 www.onsemi.com 17 equations for placement of pole, zero and crossover frequency follow: current?loop compensator voltage?loop compensator iz 1 l c vz 2 l c ip f sw 4 vp f sw 4 i 2 ip v 2 vp the implementation of the above compensators is through a resistance on the negative input (r c2 , r f1 ), resistor (r c1 , r v1 ) and capacitor (c c1 , c v1 ) in series in feedback and another capacitor (c c2 , c v2 ) in feedback of an opamp. the feedback capacitors (c c1 , c v1 ) in series with feedback resistor are chosen, on the order of less than 3 nf. the values are calculated as follows: current?loop compensator voltage?loop compensator r c1 1 iz c c1 r v1 1 vz c v1 c ce 1 ip r c1 c ve 1 vp r v1 c c2 c c1 c c1 c ce 1 c v2 c v1 c v1 c ve 1 r c2 1 i (c c1 c c2 ) r f1 1 v (c v1 c v2 ) the resistor divider on the negative input of the vea also sets the output voltage. this resistor divider is composed of a resistor from the output voltage to the negative input of the vea (r f1 ) and a resistor from the negative input of the vea to ground (r f0 ). the bottom resistor value is calculated as follows: r f0 r1 v ref v out v ref thermal considerations the power dissipation of the ncv8856 varies with the mosfets used, v in and the boost voltage (v bst ). the average mosfet gate current typically dominates the control ic power dissipation. the ic power dissipation can be estimated as follows: p ic v in i q p hs p l where: p ic : control ic power dissipation i q : ic measured supply current (quiescent current) p tg : high?side mosfet gate driver losses p bg : low?side mosfet gate driver losses the high?side switching mosfet gate driver losses are: p tg q tg f sw v bst where: q tg : total high?side mosfet gate charge at v bst v bst : bst pin voltage the low?side synchronous rectifier mosfet gate driver losses are: p bg q bg f sw v cc where: q bg : total low?side mosfet gate charge at v in the junction temperature of the controller can then be calculated as follows: t j t a p ic r ja where: t j = junction temperature of the ic t a = ambient temperature r ja = junction?to?ambient thermal resistance of the ic package the package thermal resistance (r ja ) can be obtained from the specifications section of this data sheet and a calculation can be made to determine the ic junction temperature. it should be noted that the physical layout of the board, the proximity of other heat sources such as mosfets and inductors and the amount of metal connected to the ic impact the temperature of the device. use these calculations as a guide, but measurements should be taken in the actual application.
ncv8856 www.onsemi.com 18 package dimensions case 948ab issue o dim d min max 6.60 millimeters e1 4.30 4.50 a 1.10 a1 0.05 0.15 l 0.50 0.70 e 0.65 bsc p --- 4.20 c 0.09 0.20 c1 0.09 0.16 b 0.19 0.30 b1 0.19 0.25 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.07 in excess of the lead width at mmc. dambar cannot be loacted on the lower radius or the foot of the lead. 4. dimensions b, b1, c, c1 to be measured be- tween 0.10 and 0.25 from lead tip. 5. datums a and b are are determined at datum h. datum h is loacted at the mold parting line and coincident with lead where the lead exits the plastic body. 6. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension e1 does not include interlead flash or protrusion. in- terlead flash or protrusion shall not ex- ceed 0.15 per side. d and e1 are determined at datum h. pin 1 reference d e1 0.08 a section b?b b b1 cc1 seating plane 20x b e e detail a 6.40 --- 4.30 20x 0.98 20x 0.35 0.65 dimensions: millimeters pitch soldering footprint l l2 gauge detail a e/2 detail b a2 0.85 0.95 e 6.40 bsc p1 --- 3.00 plane seating plane c h b b b m end view a-b m 0.10 d c top view side view a-b 0.20 d c 110 11 20 b a d detail b 2x 10 tips a1 a2 c 0.05 c c p p1 bottom view 3.10 6.76 20x
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